1. Field of the Invention
The present invention relates to the lateral insulation between transistors formed on a substrate of semiconductor on insulator or SOI type.
2. Discussion of Known Art
An insulation structure between two transistors of complementary type is shown in FIGS. 1A to 1D. FIGS. 1A and 1C. are to views and FIGS. 1B and ID are cross-section views along planes BB and D-D defined in FIGS. 1A and IC. The case of an SOI structure comprising a thin silicon layer 1 on a thin silicon oxide layer 2 on a silicon substrate 2 is here considered.
As illustrated in FIGS. 1A and 1B, in an integrated circuit, to define active areas. Where transistors are to be formed, trenches 4 are made to cross layers 1 and 2 and to penetrate into substrate 3. Trenches 4 further delimit wells 3a and 3b of opposite doping, shallower than trenches 4 and arranged under each of the active areas. Trenches 4 are filled with silicon oxide, commonly called field oxide 5, to form insulation walls.
As illustrated in FIGS. 1C and 1D, transistors 6 comprise, between drain and source regions 7, a conductive gate 10 insulated by a layer 8. Spacers 9 are formed on either side of the gate. Source and drain regions 7 axe formed after the gate, for example by transforming into silicide the apparent portions of this layer 1. Simultaneously, the upper portion of gate 10a is silicided.
Each of the operations resulting in the structure of FIG. 1D implies different cleanings. Cleanings are in particular involved:                on removal of the mask for defining field oxide 5,        before the forming of gate oxide layer 8,        after the forming of gate 10,        after the forming of spacers 9,        before and after the forming of silicided areas 7 and 10a. Such cleanings use acids, and especially diluted hydrofluoric acid. These acids etch field oxide 5, more specifically in regions located at the periphery of the field oxide regions. This results in the forming of cavities 11 which extend at the periphery of field oxide 5 and which may reach substrate 3, especially in the case of structures for which the thicknesses of insulator layer 2 and of semiconductor layer 1 are small. Indeed, in some technologies, such thicknesses may be as low as from 10 to 25 nm. The local disappearing of this insulator on the sides during the forming of the circuits may be the cause of multiple transistor failure modes. For example, in the forming of silicide regions 7 and 10a, a short-circuit may appear between source and drain regions 7 and wells 3a and 3b formed in substrate 3.        
To overcome this disadvantage, has been provided to for an insulation wall of the type illustrated in FIG. 2. This drawing shows trench 4 filled with an insulator 5. Further, an insulating layer 5a formed above insulator and protrudes on either side of the trench. Thus, in the various above-mentioned acid attacks, the risk for cavities going all the way to substrate 3 to be created is limited. However, this result is clearly obtained at the cost of a loss of space in the active silicon areas, which may adversely affect the transistor performance.
There thus is a need for insulation wails between transistors least overcoming some of the disadvantages of prior art walls.